Semiconductor device geometries have dramatically decreased in size since their introduction several decades ago. Modern semiconductor fabrication equipment routinely produce devices with 45 nm, 32 nm, and 28 nm feature sizes, and new equipment is being developed and implemented to make devices with even smaller geometries. The decreasing feature sizes result in structural features on the device having decreased spatial dimensions. The widths of gaps and trenches on the device narrow to a point where the aspect ratio of gap depth to its width becomes high enough to make it challenging to fill the gap with dielectric material. The depositing dielectric material is prone to clog at the top before the gap completely fills, producing a void or seam in the middle of the gap.
Over the years, many techniques have been developed to avoid having dielectric material clog the top of a gap, or to “heal” the void or seam that has been formed. One approach has been to start with highly flowable precursor materials that may be applied in a liquid phase to a spinning substrate surface (e.g., SOG deposition techniques). These flowable precursors can flow into and fill very small substrate gaps without forming voids or weak seams. However, once these highly flowable materials are deposited, they have to be hardened into a solid dielectric material.
In many instances, the hardening includes a heat treatment to remove carbon and hydroxyl groups from the deposited material to leave behind a solid dielectric such as silicon oxide. Unfortunately, the departing carbon and hydroxyl species often leave behind pores in the hardened dielectic that reduce the quality of the final material. In addition, the hardening dielectric also tends to shrink in volume, which can leave cracks and spaces at the interface of the dielectric and the surrounding substrate. In some instances, the volume of the hardened dielectric can decrease by 40% or more.
Spin-on dielectrics (SOD) have also been used to flow into features on a patterned substrate. The material is generally converted to silicon oxide from a silazane-type layer which contains silicon, nitrogen and hydrogen. Silicon, nitrogen and hydrogen containing layers are typically converted to silicon oxide at high temperature in an oxygen containing environment. Oxygen from the environment displaces nitrogen and hydrogen to create the silicon oxide layer. High temperature exposure to oxygen environments can ruin underlying layers for some circuit architectures. This consideration results in the need to stay within a “thermal budget” during a manufacturing process flow. Thermal budget considerations have largely limited SOD to process flows incorporating an underlying silicon nitride layer which can protect underlying features from oxidation (e.g. DRAM applications).
Alternative methods have been developed which deposit silazane containing layers by radical-component CVD. Radical-component CVD can create a flowable layer by exciting one precursor and combining it with an unexcited silicon-containing precursor in the plasma-free substrate processing region. Layer properties, including density, may change slightly in time until the silazane containing layer is converted to silicon oxide. Controlling the evolution of the layer properties improves the manufacturability of devices using these layers. Thus, there is a need for new deposition processes and materials to form dielectric materials which do not evolve over time. This and other needs are addressed in the present application.